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PDU54
4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54)
FEATURES
* * * * * Digitally programmable in 16 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 100K-ECL interfaced & buffered Available in 24-pin DIP (600 mil) socket or SMD
PDU54-xx DIP PDU54-xxM Military DIP
N/C N/C GND N/C N/C N/C N/C N/C GND OUT N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
data 3 delay devices, inc.
PACKAGES
IN N/C VEE A3 N/C N/C A2 A1 VEE A0 N/C N/C
N/C N/C GND N/C N/C N/C N/C N/C GND OUT N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
IN N/C VEE A3 N/C N/C A2 A1 VEE A0 N/C N/C
PDU54-xxC4 SMD PDU54-xxMC4 Mil SMD
FUNCTIONAL DESCRIPTION
The PDU54-series device is a 4-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A3-A0) according to the following formula: TDA = TD0 + TINC * A
PIN DESCRIPTIONS
IN OUT A3-A0 VEE GND Signal Input Signal Output Address Bits -5 Volts Ground
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
* * * * * * * * * Total programmed delay tolerance: 5% or 40ps, whichever is greater Inherent delay (TD0): 3.3ns typical Address to input setup (TAIS): 2.9ns Operating temperature: 0 to 85 C Temperature coefficient: 100PPM/C (excludes TD0) Supply voltage VEE: -5VDC 0.7V Power Supply Current: -300ma typical (50 to -2V) Minimum pulse width: 3ns or 10% of total delay, whichever is greater Minimum period: 8ns or 2 x pulse width, whichever is greater
A i-1 PW IN IN TDA OUT Figure 1: Timing Diagram
1997 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part Number PDU54-100 PDU54-200 PDU54-250 PDU54-400 PDU54-500 PDU54-750 PDU54-1000 PDU54-1200 PDU54-1500 PDU54-2000 PDU54-2500 PDU54-3000 Incremental Delay Per Step (ps) 100 50 200 60 250 60 400 80 500 100 750 100 1000 200 1200 200 1500 200 2000 400 2500 400 3000 500 Total Delay Change (ns) 1.50 3.00 3.75 6.00 7.50 11.25 15.00 18.00 22.50 30.00 37.50 45.00
A3-A0
Ai TOAX TAIS
NOTE: Any dash number between 100 and 3000 not shown is also available.
PW OUT
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU54
APPLICATION NOTES
ADDRESS UPDATE
The PDU54 is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation: TOAX = max { (Ai - A i-1) * TINC , 0 } where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed. conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input. When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements. Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.
INPUT RESTRICTIONS
There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended
PACKAGE DIMENSIONS
24 23 22 21 20 19 18 17 16 15 14 13
.580 MAX. .010 .002
1 2 3 4 5 6 7 8 9 10 11 12
.600 .005
1.270.010 Lead Material: Nickel-Iron alloy 42 TIN PLATE
.380 MAX.
.015 TYP. .018 TYP. .070 MAX. 1.100.010 11 Equal spaces each .100.010 Non-Accumulative
PDU54-xx (Commercial DIP) PDU54-xxM (Military DIP)
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
PDU54
PACKAGE DIMENSIONS (cont'd)
.020 TYP. .040 TYP. .010.002
24 23 22 21 20 19 18 17 16 15 14 13
.710 .590 .00 MAX.
.882 .00 .007 .00
1
2
3
4
5
6
7
8
9
10 11 12
.090 1.100 1.280.020
.100
.380 MAX.
.050 .01
PDU54-xxC4 (Commercial SMD) PDU54-xxMC4 (Military SMD)
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER Total Programmable Delay Inherent Delay Address to Input Setup Time Output to Address Change Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TDT TD0 TAIS TOAX PERIN PERIN PERIN PWIN PWIN PWIN MIN TYP 7 3.3 UNITS TINC ns ns % of TDT % of TDT % of TDT % of TDT % of TDT % of TDT
2.9 See Text 20 40 200 10 20 100
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VEE VIN TSTRG TLEAD MIN -7.0 VEE - 0.3 -65 MAX 0.3 0.3 150 300 UNITS V V C C NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 85C) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current SYMBOL VOH VOL VIH VIL IIH IIL MIN -1.025 -1.810 -1.165 -1.810 0.5 MAX -0.880 -1.620 -0.880 -1.475 340 UNITS V V V V A A NOTES VIH = MAX,50 to -2V VIL = MIN, 50 to -2V VIH = MAX VIL = MIN
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU54
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): -4.5V 0.1V Input Pulse: Standard 100K ECL levels Source Impedance: 50 Max. Rise/Fall Time: 1.0 ns Max. (measured between 20% and 80%) Pulse Width: PWIN = 10ns Period: PERIN = 100ns OUTPUT: Load: Cload: Threshold: 50 to -2V 5pf 10% (VOH + VOL) / 2 (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) OUT IN TRIG OSCILLOSCOPE
ADDRESS SELECT
Test Setup
PERIN PW IN TRISE INPUT SIGNAL
80% 50% 20%
TFALL VIH
80% 50% 20%
VIL TFALL
TRISE OUTPUT SIGNAL
50%
VOH
50%
VOL
Timing Diagram For Testing
Doc #98004
3/18/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4

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